Test Design and Optimization for Multiple Core Systems- On-a-Chip using Genetic Algorithm

Core based design has become the de-facto design style for many VLSI design houses, as it facilitates design reuse, import of specialized expertise from external vendors and leads to a more streamlined design flow. Pre-designed cores and reusable modules are popularly used in the design of large and complex Systems-on-aChip (SOC). Embedded cores such as processors, custom application-specific integrated circuits (ASIC), and memories are being used to provide SOC solutions to complex integrated circuit design problems. Traditional approaches for testing core-based SOCs completely rely on additional test structures such as boundary scan or test bus for test-data transfers to and from the core under test (CUT). Available techniques for testing of core-based SOCs do not provide a systematic means for synthesizing low-overhead test architectures and compact test solutions. Test application time and core accessibility are two major issues in SOC Testing. The test application time must be minimized, and a test access mechanism (TAM) must be developed to transport test data to and from the cores. While many different formulations of the embedded core test-scheduling problem (ECTSP) have been proposed in test literature recently, a single unified presentation of ECTSP in terms of conventional scheduling patterns has been lacking. In this paper, Integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution is proposed. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. An approach to solve the problems of Test Scheduling and Test Access Mechanism partition for SOC based on Genetic Algorithm (GA) is presented and the results are compared with other approaches already existing. The results of GA based approach are shown to be superior to the heuristic approaches proposed in the literature. Key-Words: Integrated Circuit, Genetic Algorithm, System-on-Chip, Pre-Designed Core, Test Vector, Test Access Mechanism, Application Specific Integrated Circuit, Benchmark Circuit.